System for specifying addresses by creating a multi-bit ranked ordered anchor pattern and creating next address by shifting in the direction of the superior position

ABSTRACT

An automatic addressing technique for flexibility specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern. The transform elements are passive elements, and no jumpers or settable switches are required to specify the physical addresses when configuring or reconfiguring the system.

BACKGROUND OF THE INVENTION

This invention relates to addressing techniques used for bus orientedcomputer systems. More particularly, this invention relates to anautomatic addressing technique for flexibly specifying the individualaddresses of a plurality of devices coupled to an information bus.

Bus oriented computer systems are known in which individual devicesconnected to an information bus are assigned unique addresses specifyingthe location of each device in a computer system. Typically, individualdevices are provided with a mechanical, electrical or electromechanicaldevice capable of being set to provide a unique address for the device.For example, in some known arrangements, each device is provided withjumper terminals which can be connected to an appropriate voltage (e.g.,ground) in such a manner that the voltage level on the combinedcollection of jumper terminals uniquely specifies the physical addressof that device, usually using a binary numbering system. In still otherknown system, manually actuatable switches are employed for the samepurpose. In both types of arrangement, the specification of a uniquedevice address requires that a user, usually a technician, manipulatethe address specifying device, which creates the possibility for humanerror in initially configuring the system. In addition, to reconfiguresuch a system, for example by adding more bus devices, the user mustcheck the setting of each device (or a master list on which theindividual addresses are recorded) in order to ensure that the newaddresses to be assigned to the additional devices do not duplicatealready used addresses.

Still other systems employ active electronic devices capable ofresponding to interrogation from a host computer by setting a deviceaddress generated by the host computer and transmitted thereto over theinformation bus. Such arrangements require additional active electroniccircuits in the bus devices, and also require special programmingcapability in the host computer to generate the individual deviceaddress values and transmit such values to the individual bus devices.Also required is a routine for establishing that an address transmittedto a device was correctly received and stored by that device. This typeof arrangement required a relatively sophisticated programming approachand is prone to both software and signaling errors.

SUMMARY OF THE INVENTION

The invention comprises an automatic addressing technique for specifyingthe individual unique addresses of an array of devices which isrelatively simple and inexpensive to implement, highly reliable inoperation, capable of establishing any address sequence required in agiven application, and highly compatible with highly configurablecomputer system.

From a first aspect, the invention comprises a method of specifying thephysical address of a plurality of devices each requiring a uniqueaddress in an array, the method including the steps of selecting theindividual desired address sequence, creating an anchor patternrepresenting an initial device address, the anchor pattern having aplurality of multi-bit rank ordered fields each having a superior endposition and an inferior end position, creating a bit patternrepresenting the next address in the sequence by shifting the bitpattern in each field in the direction of the superior end position ofthat field by an integral multiple (preferably unity) of one rank andrelocating the superior end rank position bit of the pattern to theinferior end rank position, and continuing the step of creating a bitpattern representing the next address until the last address in thesequence is attained. For an anchor pattern comprising N bits, thenumber of the fields can range from N to i, where i is the minimumnumber of bits required to uniquely specify a total number of J devices.Each address is specified with a bit of predetermined rank from each ofthe i fields.

From an apparatus standpoint, the invention comprises a multiconductorbus device for specifying a unique physical address for each of aplurality of J devices in an array in accordance with a desired addresssequence, the bus device comprising N conductors arranged in paralleland grouped into i fields, where i is the minimum number of bitsrequired to uniquely specify J devices, each field having a plurality ofrank ordered bits with a superior end position and an inferior endposition, the physical address for each device being determined by i bitvalues selected from one conductor of each field, and a plurality oftransform elements each having an input coupled to the N conductors forconverting a physical device address presented at the input thereto tothe next physical device address at the output thereof, each transformelement including means for shifting the bit pattern in each field of aphysical device address presented at the input by an integral multiple(preferably unity) of one rank and relocating the superior end rankposition bit of the input address to the inferior rank position of theoutput address. The number of bit values i used to determine thephysical address for each device may be increased up to a value of N, ifdesired, to create additional potential address sequences.

Each transform element preferably comprises a plurality of N inputterminals, a plurality of N output terminals and a plurality of Nconductive paths coupled between the input terminals and the outputterminals, one path coupling the input terminal corresponding to thesuperior end rank position of each field to the output terminal locatedat the inferior rank position of the corresponding field.

From a different method aspect, the invention comprises a method ofproducing a multi-bit anchor pattern capable of transformation into adesired sequence of physical device addresses, each address comprising aplurality of bits each selected from a different one of a plurality ofrank ordered multi-bit fields, each bit in each address corresponding toa preselected rank in the associated multi-bit field. The methodproceeds by selecting a desired address sequence, converting eachaddress of the desired sequence to a multi-field binary equivalenthaving a number of fields equal to the number of bits comprising eachaddress, and arranging the bits in each binary equivalent field in asequential order related to the manner in which the anchor pattern istransformed into the desired sequence of physical device addresses.

The invention provides a highly reliable device addressing capabilitywhich is extremely simple to implement, requiring only passiveelectrically conductive paths arranged in a repeated predeterminedpattern in order to effect the sequential address transformations. Sincethe desired sequence can be unlimited, the invention is extremely usefuland effective is bus oriented computer systems which are intended to behighly configurable. Moreover, the specification of a desired addresssequence is completely determined once the anchor pattern has beenestablished for a given desired sequence.

For a fuller understanding of the nature and advantages of theinvention, reference should be had to the ensuing detailed descriptiontaken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the preferred embodiment ofthe invention;

FIG. 2 illustrates the address transform element used in the preferredembodiment;

FIG. 3 illustrates the anchor pattern required to effect a first addresssequence; and

FIGS. 4 and 5 illustrate other anchor patterns required to effect twodifferent address sequences.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Turning now to the drawings, FIG. 1 is a schematic diagram illustratingthe invention as implemented in conjunction with a Small ComputerSystems Interface (SCSI) bus system. The SCSI bus standards are definedin ANSI document X3.131, the disclosure of which is hereby incorporatedby reference. As seen in this figure, a SCSI bus generally designatedwith reference numeral 10 has a conventional terminator 12 coupled toeach end thereof, and a plurality of computer devices coupled togetherin a serial or daisy-chain configuration. The first such device is aninitiator 14, typically a computer. The remaining seven devices aretarget devices, usually storage devices (such as disc drives or tapedrives) 15-21.

The SCSI bus 10 is supplemented by a multi-bit address bus generallydesignated with reference numeral 25 which conveys physical deviceaddresses. Bus 25 is coupled to a host device (not illustrated) whichgenerates a multi-bit character termed an anchor pattern, which isapplied to one end of bus 25, for example upper end 27 illustrated inFIG. 1. Each bus device 14-21 is coupled to address bus 25, and addressbus 25 includes a plurality of anchor pattern transform elements 28 atlocations intermediate the connection points of the SCSI bus devices14-21 to the address bus 25. In the specific embodiment illustrated inFIG. 1 and described below, each SCSI bus device 14-21 is connected tothe same three conductors within address bus 25, these connection pointsbeing termed the tap points. Since the addressing scheme is a binarybased system, three lines, each corresponding to a bit of addressinformation, are the minimum required to uniquely specify eightdifferent devices. Also, for reasons explained more fully below,fourteen conductors are used in address bus 25 to generate any one of alarge number of desired sequences of physical device addresses 0-7 inthe FIG. 1 system.

FIG. 2 illustrates the address transform element 28 used in theembodiment of FIG. 1. In FIG. 2, the fourteen conductors within addressbus 25 are ordered 0-13, as indicated, and the three tap connections aretaken from conductor Nos. 1, 4 and 10. As will become more evidentbelow, the three bit address is composed of three fields: the firstfield comprised of conductors 0 and 1, a second field composed ofconductors 2-5, and a third field composed of conductors 6-13. As willbe appreciated by those skilled in the art, these fields correspond tothe 2⁰, 2¹ and 2² fields, respectively, of a three bit binary number. Ineach transform element 28, the conductors in each field are connected toeffect a one order shifting of each conductor in a fixed direction,field by field, with the last conductor in the direction of the shiftbeing coupled back to the first conductor in the field. This may be mostreadily understood by referring to the 2² field comprising conductors6-13. The input side of conductor 13 emerges from transform element 28as conductor 12, 12 emerges as 11, 11 emerges as 10, etc. Thus,conductors 13-7 are effectively right shifted one rank in this field.Conductor 6, which is the edgemost conductor in the shifted direction(right), emerges as conductor 13 on the output side. Thus, the fieldcomposed of conductors 6-13 is shifted right by one rank, with the endconductor in the direction of the shift, hereinafter termed the superiorend position, relocated to the opposite end of the rank, termed theinferior end position.

Similarly, in the field composed of conductors 2-5, conductors 3, 4 and5 are right shifted between the input side and the output side, and thesuperior end conductor (conductor 2) is relocated to the inferior endposition (as emerging conductor 5).

The same transform is effected on the conductors in the fields composedof conductors 0 and 1; however, since there are only two conductors, theshifting and relocation of the superior end conductor to the inferiorend position merely requires the transposition of the two conductors 0and 1.

As noted above, each transform element 28 in the address bus 25 has theidentical configuration to that just described with reference to FIG. 2.

An important feature of the invention is the addressing flexibilityafforded by the transform elements 28 when combined with the anchorpattern selection described below. In essence, the SCSI bus devices14-21 can be assigned physical addresses in a wide variety of differentsequential address orders by selecting the correct anchor pattern. Forexample, SCSI bus devices 14-21 may simply be addressed in their orderof physical proximity to anchor terminal 27, designating initiator 14with address 0, target device 15 with address 1, target device 16 withaddress 2, etc.

FIG. 3 illustrates the anchor pattern required to effect this particularaddress sequence. In this figure, the bus conductors are numbered in thesame order as that described above with reference to FIG. 2 and thethree field grouping is indicated by the vertical separation lines.Also, the tap locations 0-7 corresponding to the SCSI bus devices 14-21are indicated in the leftmost column. The anchor pattern is the patternto the immediate right of tap location 0 and the transformed patterns attap locations 1-7 are sequentially presented in rows from top to bottomof the figure. The three tap lines are chosen in this example areconductor Nos. 1 (field 0), 4 (field 1) and 10 (field 2), which is thesame tap arrangement as that depicted in FIG. 2. Thus, at tap location0, the designated three bit address is binary 000, which corresponds to0 decimal. At tap location 1, the three bit address is 001, which isdecimal 1, the three bit address at tap location 2 is binary 010corresponding to decimal 2, etc. Thus, by applying a 14-bit anchorpattern of 00001111001101, the address sequence 0-7 is obtainedautomatically by virtue of the transform operation effected on the14-bit pattern by each transform element 28.

The manner in which the anchor pattern is established is as follows.Initially, the desired decimal address sequence is selected. Next, theaddress sequence is decomposed into a three-digit binary numbercomprised of the field components 2²+2¹+2⁰. For the 14-bit patternexample under discussion, the pattern of each binary field must bechecked for compliance with two specific rules. First, the 2₁ sequencemust repeat every four bits. Second, the 2⁰ sequence must alternateevery bit. If the sequence does not satisfy both rules, another sequencemust be chosen until a sequence is found which does comply.

Once a sequence which satisfies both rules is found, the bit sequencefor the 2² field is laid out across bits 6-13 of the anchor pattern(corresponding to bus 25 conductors 6-13) starting at the tap bit andproceeding in the opposite direction of the shift effected by thetransform elements 28. Since the transform element 28 produces a rightshift, the bit sequence is laid out from right to left, starting at thetap bit, wrapping from bit position 13 to the first bit position in the2² field (bit 6) and finishing at bit 9. Next, the bit sequence for the2¹ field is laid out across bits 2-5 from the anchor pattern, startingat the tap bit in the same manner as in the previous layout for the 2²field. Only four bits are required, since the pattern repeats after fourbits (rule 1). Lastly, the two bits of the 2⁰ field are laid out acrossbits 0 and 1 of the anchor pattern starting at the tap bit in the samemanner as in the previous steps. Only two bits are required since thepattern alternates (rule 2). The anchor pattern is now completelydetermined.

The following is an example of the construction of an anchor pattern forthe desired address sequence 3, 4, 5, 2, 7, 6, 1, 2. This is sequence isfirst decomposed into a three-digit binary number comprised of thecomponents 2²+2¹+2⁰:

2²=>0, 1, 1, 0, 1, 1, 0, 0

2¹=>1, 0, 0, 1, 1, 0, 0, 1

2⁰=>1, 0, 1, 0, 1, 0, 1, 0

Next, the binary number is checked to see whether the sequence satisfiesrules 1 and 2. The 2¹ sequence does repeat every four bits, and the 2⁰sequence does alternate every digit. Consequently, the bit sequencelayout may commence. For the 2² sequence, the first bit in the sequence(0) is placed at the tap location (bit 10) and the succeeding bits inthe sequence are laid out as described above. The resulting bit sequenceis as follows:

Next, the four bits of the 2¹ sequence are laid out across bits 2-5 ofthe anchor pattern beginning at tap bit 4 and proceeding in the oppositedirection of the transform. The result is as follows:

Lastly, the first two bits of the 2⁰ sequence is laid out across bits Oand 1 of the anchor pattern starting at the tap bit 1. The completedanchor pattern and the patterns resulting from the successivetransformations of the anchor pattern are shown in FIG. 4. By checkingthe values for each row in tap position 1, 4 and 10, it can be seen thatthe desired address sequence has been obtained.

As noted above, with the 14-bit anchor pattern implemented in thearrangement of FIG. 1, there are some sequences which cannot be chosendue to the constraints imposed by the choice of fields 2⁰ and 2¹ ofdiminished size from field 2². Where additional potential sequences arenecessary or desirable, the size of field 2⁰ or field 2¹ or both fieldscan be increased. For example, field 0 can be increased to a three-bitfield, field 2¹ can be increased to a seven-bit field or the like. Inorder to provide all possible sequences, the anchor pattern should beexpanded to three fields of eight bits each. However, where not allpossible sequences are required, it is convenient to reduce the numberof bus conductors or to reduce the number of the required tapconnections and the size of the address bus 25.

The following illustrates how a desired address sequence which cannot beconverted to a proper anchor pattern using the 14-bit implementation maybe converted into a usable anchor pattern in a 24-bit anchorimplementation.

The desired address sequence of 1, 3, 5, 7, 0, 2, 4, 6 is decomposedinto a three-digit binary number comprised of the components 2²+2¹+2⁰.

2²=>0, 0, 1, 1, 0, 0, 1, 1

2¹=>0, 1, 0, 1, 0, 1, 0, 1

2⁰=>1, 1, 1, 1, 0, 0, 0, 0

Checking the binary numbers against the rules, rule 1 is satisfied sincethe 2¹ sequence does repeat every four bits. However, the 2⁰ sequencedoes not alternate every digit and the sequence cannot be constructedusing a 14-bit pattern.

Taking the same sequence, and selecting a 24-bit anchor pattern, theanchor pattern layout proceeds as follows. No rule checks are necessarywith a 24-bit pattern, since all patterns can be implemented.Consequently, the bit sequence for the 2² sequence is first laid out ina similar fashion to that described above starting at the tap bit(position 19 in this case) and proceeding in the opposite direction ofthe transform (i.e., right to left), wrapping from 23 to 16, andfinishing at bit 18. The resulting bit sequence is as follows:

Next, the bit sequence for the 2¹ sequence is laid out across bits 15-9of the anchor pattern starting at the tap bit (position 9). The resultis as follows:

Lastly, the bit sequence of the 2⁰ field is laid out across bits 7-0 ofthe anchor pattern starting at the tap bit (position 4). The completeanchor pattern, and the remaining transformations are shown in FIG. 5.The sequence can be checked row by row and compared to the desiredsequence.

As will now be apparent, the invention affords a highly flexibleaddressing arrangement for an array of devices which is particularlysuited for highly configurable computer systems. Further, the inventioncan be implemented in a relatively straightforward and simple fashionusing essentially only passive devices (the tap connections and thetransform elements 28), which can be prefabricated and tested prior toinstallation. Once connected, the desired address sequence is selected,is converted to a suitable anchor pattern, and the desired addressingsequence is automatically provided to the individual devices connectedto the information bus.

Implementation of the transform elements 28 can be accomplished in anumber of ways. Firstly, the address bus can be incorporated intosuitable cables, such as flat flexible cables, and the conductivepatterns required to shift and rotate the individual conductor lines canbe formed within the cable itself. Alternatively, the transform elementsmay be individual bridge connector elements incorporating the shift androtate wire patterns and provision may be made to insert such discreetdevices into the address bus path. Still further, individual segments ofinformation bus 10 may be implemented as fixed length multiple conductorpaths on substrates in close proximity to the bus devices 14-21 and, insuch applications, the transform elements 28 can be incorporated intoportions of such substrates along with appropriate connectors to routethe address bus conductors to the input portion of the transformelements 28 and to route the output conductors from the transformelements 28 back to the address bus 25.

While the above provides a full and complete disclosure of the preferredembodiments of the inventions, various modifications, alternateconstructions and equivalents may be employed, as desired. For example,anchor patterns with different numbers of bits per field, as well asdifferent numbers of fields, may be selected and employed, depending onthe address requirements of a particular application. Therefore, theabove description and illustrations should not be construed as limitingthe scope of the invention which is defined by the appended claims.

What is claimed is:
 1. A method of specifying the physical address of aplurality of devices each requiring a unique address in an array, saidmethod comprising the steps of: (a) selecting the individual a desiredaddress sequence; (b) creating an anchor pattern representing an initialdevice address, said pattern having a plurality of multi-bit rankordered fields each having a superior end position and an inferior endposition; (c) creating a bit pattern representing the next address inthe sequence by shifting the bit pattern in each field in the directionof the superior end position of that field by an integral multiple ofone rank and relocating the superior end rank position bit of thepattern to the inferior end rank position; and (d) continuing step (c)until the last address in the sequence is attained wherein each bit thatis shifted beyond the superior end position is rotated back to theinferior bit position.
 2. The method of claim 1 wherein the integralmultiple in step (c) is unity.
 3. The method of claim 1 22wherein saidstep (d)the said step of creating a bit pattern is performed a number oftimes equal to J−2, where J is the total number of a plurality ofdevices.
 4. The method of claim 1 22wherein said anchor patterncomprises N bits and the number of said field is i, where i is theminimum number of bits required to uniquely specify J devices.
 5. Themethod of claim 4 wherein N≧i.
 6. The method of claim 4 wherein N=i. 7.The method of claim 4 further including the step of specifying eachaddress with a bit of predetermined rank from each of the i fields.
 8. Amulticonductor bus device for specifying a unique physical address foreach of a plurality J of devices in an array in accordance with adesired address sequence, said bus device comprising: N conductorsarranged in parallel and grouped into i fields, where i is the minimumnumber of bits required to uniquely specify J devices, each field havinga plurality of rank ordered bits with a superior end position and aninferior end position, the physical address for each device beingdetermined by i bit values selected from one conductor of each field;and a plurality of transform elements each having an input and an outputcoupled to said N conductors for converting a physical device addresspresented at the input thereto to the next physical device address inthe desired address sequence at the output thereof, each transformelement including means for shifting the bit pattern in each field of aphysical device address presented at the input by an integral multipleof one rank and means for relocating the superior end rank position bitof the input address to the inferior rank position of the next physicaldevice address .
 9. The invention of claim 8 wherein said integralmultiple is unity.
 10. The invention of claim 8 wherein N≧i.
 11. Theinvention of claim 8 wherein N=i.
 12. The invention of claim 8 whereineach transform element comprises a plurality of N input terminals, aplurality of N output terminals and a plurality of N conductive pathscoupled between said input terminals and said output terminals, one pathcoupling the input terminal corresponding to the superior end rankposition of each field to the output terminal located at the inferiorrank position of the corresponding field, the remaining paths effectingthe bit pattern shift.
 13. A method of producing an anchor patterncapable of being transformed into a desired sequence of physical deviceaddresses each comprising a plurality of bits each selected from adifferent one of a plurality of rank ordered multi-bit fields, saidmethod comprising the steps of: (a) selecting a desired addresssequence; (b) converting each address of the desired sequence to amulti-field binary equivalent having a number of fields equal to thenumber of bits comprising each address, each field having a number ofbits relatively prime to the number of bits in the preceding field; and(c) arranging the bits in each binary equivalent field in a sequentialorder related to the manner in which the anchor pattern is transformedinto the desired sequence of physical device addresses.
 14. The methodof claim 13 wherein said anchor pattern comprises N bits and the numberof said fields is i, where i is the minimum number of bits required touniquely specify J devices.
 15. The method of claim 14 wherein N≧i. 16.The method of claim 14 wherein N=i.
 17. The method of claim 14 furtherincluding the step of specifying each address with a bit ofpredetermined rank from each of the i fields.
 18. A transform elementcomprising: (a) a plurality of rank order inputs grouped into fields;and (b) a plurality of rank ordered outputs grouped into the fields,each field having a superior end position and an inferior end position,wherein each rank ordered input within a field is operatively coupled toa rank ordered output shifted in that same field by an integral multipleof one rank such that each bit of the output that is shifted beyond thesuperior end position of each field is rotated back to the inferior bitposition.
 19. The transform element of claim 18, wherein an input istapped for connecting a device.
 20. The transform element of claim 18,wherein the integral multiple is unity.
 21. The transform element ofclaim 20, wherein an input is tapped for connecting a device.
 22. Themethod of claim 2, wherein the step of creating further includesrelocating the superior end rank position bit of the pattern to theinferior end rank position.
 23. The method of claim 22, wherein the stepof creating is repeated to create additional addresses in the sequence.24. The method of claim 8, wherein I is the minimum number of bitsrequired to uniquely specify J devices.